The present invention derives from the development of a management device (Power Management) designed to reduce to a minimum the power consumption in portable electronic instruments provided with batteries, such as for example cellular phones or portable computers, and the description hereinbelow makes reference to this specific field of application to simplify the illustration without limiting the invention to these applications. Discussion of steps well know to those skilled in the art has been abbreviated or eliminated for brevity.
The above device is substantially an interface between a battery charger and the main battery of the portable electronic instrument. The main task of this device is that of controlling the charge of the battery.
Further on, other tasks are referable to the above mentioned device, such as: the continuous monitoring of the battery voltage, the charge and the monitoring of the backup battery, and the management of the consumption during the different operational states of the portable electronic instrument.
In this specific field of application, the requirement of reducing to the minimum the consumption of the integrated circuits incorporated in the portable electronic instrument and supplied by batteries is particularly felt.
The controllers employed in the prior art for this purpose in the modern cellular phones use a very high number of level shifter devices in order to manage at least three different independent power supplies, by interfacing with the digital portion of the (Universal Energy Management) UEM device, which operates with different power supplies.
In FIG. 1, a level shifter 20 with differential cell of known type is shown as an example, which is supplied between a first reference 21 of voltage Vout and a second reference GND. The shifter 20 has two signal input terminals 22 and 23 and an output terminal OUT.
The power supply Vout corresponds to the value of voltage produced on the output terminal OUT. The first input 22 receives a voltage signal VIN, while the second input 23 receives a signal IN.
As an example, if the signal IN on the input 23 is at the logic value "1", the NMOS transistor M1 is off (because the signal IN is inverted to a logic 0 by an inverter prior to presenting it to the gate of the transistor M1) and the NMOS transistor M2 is on, thereby pulling the node B to ground. Accordingly, the PMOS transistor M4 is on and brings the node A to a potential value equal to that of the power supply VOUT. The output OUT has therefore the logic value "1", although it is translated into the value of the power supply VOUT.
If the signal VIN is annulled or off, then also the signal IN is brought to zero in such a way that a voltage value equal to 0V is applied to each of the gate terminals of the transistors M1 and M2. In such a condition, both the nodes A and B remain floating and therefore can position themselves in an indefinite state, thus not ensuring in output the desired logic signal "0", to be compared with the above mentioned values of voltage in input.
The prior art already proposes a solution in order to solve the problem. Such solution consists in utilizing a "pull-up" component 25 on the node B so as to force the voltage at that point to the value of the power supply VOUT when the signal VIN is not present, in order to guarantee the logic state "0" on the output OUT in these conditions. Such a "pull-up" component can be formed in many ways, for example by means of a resistance or with a current generator, as shown in FIG. 2.
Though advantageous from some points of view, this solution presents also some drawbacks, the most serious of which is that in normal conditions of operation there is a considerable consumption of current I from the power supply to the output. Essentially there is a strong consumption of current I when, in conditions of normal operation, the transistor M2 is on.
Furthermore, the current I must be high enough to ensure that, when the signal VIN becomes null, the node B rapidly achieves the value of VOUT in order to avoid a cross conduction between the transistor M3 and the transistor M2 which form an inverter. This represents therefore a constraint against the actual reduction of such current I.